1. Field of the Invention
The present invention relates to a semiconductor memory device that is capable of assigning the read time of data stored in memory cells. For example, the invention relates to a semiconductor memory device that controls the read time in terms of latency whose units are defined as the number of cycles of an externally applied clock.
2. Description of the Related Art
Among recent semiconductor memory devices, there is one that can externally assign the read time from the time that the read instruction is given until data stored in a memory cell is read out and is output from the semiconductor memory device. In particular, for synchronous mask ROM (synchronous mask read only memory), SDRAM (synchronous dynamic random access memory) and the like, whose operations are synchronized to the clock of the system that the semiconductor memory devices are used in, a term xe2x80x9clatencyxe2x80x9d, which denotes the aforementioned read time by the number of clock cycles, is used.
By enabling latency to be externally assigned like this, it is possible to set the most appropriate read time according to the performance of the semiconductor memory device itself, the requirements of the system, and the user""s application. That is to say, since the read time required by the semiconductor memory device is determined by the interrelationship between the semiconductor memory device and the system, there is a requirement that the read time be flexibly controlled depending on various conditions. For example, in recent years the operating frequencies of systems have been increasing, however, the reality is that the performance of semiconductor memory devices has not been keeping pace with the operating speed of systems. Consequently, in such a situation, it is necessary to bridge the performance gap that exists between systems and semiconductor memory devices, by assigning a large value of latency.
As an example of a semiconductor memory device used heretofore, synchronous mask ROM reads out data stored in memory cells as follows. Latency from CAS (column address strobe) signal active to valid data output, termed xe2x80x9cCAS latencyxe2x80x9d is set externally from the synchronous mask ROM. Here, CAS latency may be abbreviated to xe2x80x9cCLxe2x80x9d in figures to be referred to in the descriptions hereunder and this description. In the case where reading is actually performed, first, a row address is assigned, the RAS (row address strobe) signal is activated, and the word line corresponding to the given row is address is activated.
Next, a column address is assigned, and the CAS signal is activated to select the digit line (also referred to as the bit line or data line) corresponding to the given column address. As a result, a unique memory cell that is specified by the row address and the column address is selected. Furthermore, as the CAS signal is active, the sense amplifier activation signal is made active to put the sense amplifier into an operational condition, and the sense amplifier senses the data stored in the memory cell via the selected digit line. The result sensed by the sense amplifier is output from the synchronous mask ROM via an output buffer or the like. Here, with conventional synchronous mask ROM, the sense amplifier activation signal is generated by utilizing a delay circuit and the like incorporated therein, and hence the period that the sense amplifier activation signal is valid is always constant.
Here, FIG. 10 is a timing diagram showing the operation of the aforementioned conventional synchronous mask ROM. In the figure, timing from the time that the CAS signal becomes active to the time that data output is completed is shown for several values of CAS latency. Furthermore, xe2x80x9cCLKxe2x80x9d shown in the figure is a clock inside the synchronous mask ROM, which is synchronized to the system clock. For example, in the case where the CAS latency is xe2x80x9c5xe2x80x9d, the sense amplifier activation signal is activated [in other words, is set to xe2x80x9cLxe2x80x9d (low level)] immediately after the CAS signal is issued at the rising edge of the zeroth clock pulse of the clock CLK, and is deactivated [in other words, is set to xe2x80x9cHxe2x80x9d (high level)] immediately after the rising edge of the second clock pulse.
Then, data output is started around the falling edge of the fourth clock pulse, and at the rising edge of the fifth clock pulse when time corresponding to CAS latency xe2x80x9c5xe2x80x9d has passed since the CAS signal was given, a first data xe2x80x9cD0xe2x80x9d which is to be burst output becomes definite and is output outside as output data. Similarly to that mentioned above, also in cases other than CAS latency xe2x80x9c5xe2x80x9d due to different values of CAS latency, in the case where CAS latency is xe2x80x9c6xe2x80x9d through xe2x80x9c8xe2x80x9d, the value of data xe2x80x9cD0xe2x80x9d becomes definite at the rising edges of the sixth clock pulse through the eighth clock pulse. In such a way, with conventional synchronous mask ROM, whatever value is assigned to CAS latency, the valid period of the sense amplifier activation signal is always two cycles of clock CLK, which is constant.
In contrast to the abovementioned synchronous mask ROM, to give one example where the active period of the sense amplifier activation signal is varied depending on CAS latency, is an SDRAM that is disclosed in Japanese Unexamined Patent Application, First Publication No. 10-69770. This SDRAM is designed with a precondition that the operating frequency gets lower as the CAS latency value decreases. In this case, the period of each clock cycle becomes longer as the CAS latency value decreases. Accordingly, in the case where the CAS latency value is decreased, the active period of the column line select signal corresponding to the access period of the memory cells and the active period of a short signal corresponding to the equalizing period of the digit line are both lengthened.
That is to say, the arrangement is such that the ratio of the active period of the column line select signal to the active period of the short signal is always approximately constant, independent of CAS latency, and also the sum of these two periods is always equal to one cycle of the system clock, independent of CAS latency. To describe the abovementioned with specific numerical values, in the case where the CAS latency is xe2x80x9c2xe2x80x9d through xe2x80x9c4xe2x80x9d, the clock cycle times are xe2x80x9c9 nsxe2x80x9d, xe2x80x9c7 nsxe2x80x9d and xe2x80x9c6 nsxe2x80x9d respectively. At this time, the active periods of the column line select signal are xe2x80x9c6 nsxe2x80x9d, xe2x80x9c4.6 nsxe2x80x9d and xe2x80x9c4 nsxe2x80x9d respectively, and the active periods of the short signal are xe2x80x9c3 nsxe2x80x9d, xe2x80x9c2.4 nsxe2x80x9d and xe2x80x9c2 nsxe2x80x9d respectively.
From the above, with an existing synchronous mask ROM, a delay circuit and the like is used to generate the sense amplifier activation signal. Therefore, whatever value the CAS latency may be, the active period of the sense amplifier activation signal has been constant. Accordingly, with the abovementioned synchronous mask ROM, timing must be designed based on the smallest value of CAS latency (xe2x80x9c5xe2x80x9d in the range shown in FIG. 10).
However, for values of CAS latency other than this, considering the case of CAS latency being xe2x80x9c8xe2x80x9d for example, data may be output for the first time at the rising edge of the eighth clock pulse. That is to say, the active period of the sense amplifier activation signal may not necessarily be two cycles, but may be longer than that. The greater the CAS latency value is, the longer the active period of the sense amplifier activation signal might be extended. In that sense, it can be said that with conventional synchronous mask ROM, the timing design was very inefficient.
If the active period of the sense amplifier activation signal is always constant, the operating margin of the sense amplifier when reading out data stored in memory cells is always the same whatever the value of CAS latency. By having an operating margin on the sense amplifier, it is possible to increase the operating frequency of the synchronous mask ROM by a corresponding amount. However, there is a problem in that with a synchronous mask ROM like that mentioned above, whatever the CAS latency may be set to, reading can in be performed only at the same operating frequency.
On the other hand, with the SDRAM mentioned above, also including the case where the CAS latency is other than xe2x80x9c1xe2x80x9d, since the sum of the active period of the column line select signal and the active period of the short signal is equal to one cycle of the clock, data stored in the memory cell is read within the period of the first clock pulse. However, in this case also, if the CAS latency is, for example, xe2x80x9c4xe2x80x9d, data is output for the first time at the timing of the fourth clock pulse. Consequently, in the case where the CAS latency is other than xe2x80x9c1xe2x80x9d, compared with when the CAS latency is xe2x80x9c1xe2x80x9d, both the active period of the column line select signal and the active period of the short signal must be able to be further extended.
In such a way, with the abovementioned SDRAM also, the timing design is similarly inefficient to the existing synchronous mask ROM. That is to say, with the abovementioned SDRAM, as the operating frequency becomes higher, the value of CAS latency is increased, and read time must be able to be lengthened. Nevertheless, as the operating frequency is increased, the active period of the column line select signal and the active period of the short signal are shortened. As a result, in the case where the operating frequency is low, an operating margin can be obtained. However, as the operating frequency becomes higher, there is a corresponding reduction in read margin, and hence there is a tendency towards unreliability.
Accordingly, an object of the present invention is to provide a semiconductor memory device that can ensure adequate margin for reading by effectively utilizing the period corresponding to CAS latency assigned externally.
A semiconductor memory device of the present invention is provided with a latency length setting circuit for variably setting latency length, being a period from the time that an instruction to read data stored in a memory cell is performed to when the data is read out from the memory cell and output outside, and a control circuit for controlling such that the read operating period from when the instruction to read data is performed to when reading of the data is completed is proportional to the latency length.
In this manner, as the latency length increases, the operating period for reading becomes longer, and hence the operating margin when reading can be ensured to that extent. Consequently, even in the case where the operating frequency is increased, by increasing the latency length the timing can have adequate margin, hence enabling the operating frequency to be further increased.
With the present invention, the read operating period may be synchronized to a clock signal used to determine the latency length. By doing so, even if the operating frequency is changed, the cycle of the clock signal changes along with it. Therefore, the read operating period can be automatically extended and contracted to synchronize it to the cycle of the clock signal.
Furthermore, with the present invention, the read operating period may be set based on data of the latency length applied to the address signal lines for assigning read addresses. By doing so, signal lines for inputting address signals can be utilized to set the latency length, so that special signal lines for setting the latency length do not need to be installed.
Moreover, with the present invention, during the sense amplifier activation period for activating sense amplifiers, depending on the currents flowing in the memory cell and reference cell inside the sense amplifier, the difference between the voltages applied to the differential input terminals of a differential amplifier inside the sense amplifier may increase with time. By doing so, the longer the sense amplifier activation period becomes in proportion to the latency length, the wider the voltage difference between the memory cell, being the object to be read out, and the reference cell becomes, which is advantageous to reading.
Moreover, with the present invention, the read operating period may be set to the period obtained by subtracting the output period, being the period from when reading is completed to when the data stored in the memory cell is output outside, from the latency length. By doing so, while consideration is given that the access time is not rate-limited by the output time, the read operating period can be ensured as long as possible. Consequently, it is possible to maximize the read margin.